`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/05/06 14:44:43
// Design Name: 
// Module Name: decode_8b10b
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module decode_8b10b(
	input  	[9:0] 	in,
	input  			clk,
	input 			rst,
	output    reg	ko,
	output 	[7:0] 	out
    );

reg    ai,bi,ci,di,ei,ii;
reg		fi,gi,hi,ji; 
//wire   ko;
reg    ho,go,fo;
reg    eo,do,co,bo,ao;

wire   aneb,cned;
wire   p13,p31,p22;
wire   ika,ikb,ikc;
wire   eei;
wire   or121,or122,or123,or124,or125,or126,or127;
wire   xa,xb,xc,xd,xe;
wire   ior134;
wire   or131,or132,or133,or134;
wire   xf,xg,xh;
wire   [7:0] out;

always @ (posedge clk or negedge rst)
		begin
				if (!rst)
						begin
								ai<=1'b0;
								bi<=1'b0;
								ci<=1'b0;
								di<=1'b0;
								ei<=1'b0;
								ii<=1'b0;
								fi<=1'b0;
								gi<=1'b0;
								hi<=1'b0;
								ji<=1'b0;
						end
				else
						begin
								ai<=in[0];
								bi<=in[1];
								ci<=in[2];
								di<=in[3];
								ei<=in[4];
								ii<=in[5];
								fi<=in[6];
								gi<=in[7];
								hi<=in[8];
								ji<=in[9];
						end
		end  

assign  aneb  =  ai ^	bi ;
assign  cned  =  ci ^	di ;
assign 	p13   =	(aneb & (~ ci & ~ di)) | (cned & (~ ai & ~ bi)) ;
assign  p31   =	(aneb & ci & di) | (cned & ai & bi) ;
assign  p22   =	(ai & bi & (~ ci & ~ di)) | (ci & di & (~ ai & ~ bi)) | (aneb & cned) ;

assign  ika	  = (ci & di & ei & ii) | (~ ci & ~ di & ~ ei & ~ ii) ;
assign	ikb   =  p13 & (~ ei & ii & gi & hi & ji) ;
assign	ikc   =  p31 & (ei & ~ ii & ~ gi & ~ hi & ~ ji) ;

always @ (posedge clk or negedge rst)
		begin
				if (!rst)
						begin
								ko <= 0;
						end
				else
						begin
								ko <= ika | ikb | ikc;
						end
		end
	
assign  eei   =  ei ^~ ii ;
assign	or121 = (p22 & (~ ai & ~ ci & eei))	| (p13 & ~ ei) ;
assign	or122 = (ai & bi & ei & ii) | (~ ci & ~ di & ~ ei & ~ ii)	| (p31 & ii) ;
assign	or123 = (p31 & ii)	| (p22 & bi & ci & eei) | (p13 & di & ei & ii) ;
assign	or124 = (p22 & ai & ci & eei) | (p13 & ~ ei) ;
assign	or125 = (p13 & ~ ei)	| (~ ci & ~ di & ~ ei & ~ ii) | (~ ai & ~ bi & ~ ei & ~ ii) ;
assign	or126 = (p22 & ~ ai & ~ ci & eei)	| (p13 & ~ ii) ;
assign	or127 = (p13 & di & ei & ii)	| (p22 & ~ bi & ~ ci & eei) ;
	
assign	xa = or127  | or121 | or122 ;
assign	xb = or122	| or123 | or124 ;
assign	xc = or121	| or123 | or125 ;
assign	xd = or122	| or124 | or127 ;
assign	xe = or125	| or126 | or127 ; 
	
always @ (posedge clk or negedge rst)
		begin
				if (!rst)
						begin
								ao<=1'b0;
								bo<=1'b0;
								co<=1'b0;
								do<=1'b0;
								eo<=1'b0;
						end
				else
						begin
								ao<=xa ^ ai;
								bo<=xb ^ bi;
								co<=xc ^ ci;
								do<=xd ^ di;
								eo<=xe ^ ei;
						end
		end	
	
assign	ior134 = (~ (hi & ji))	& (~ (~ hi & ~ ji))	& (~ ci & ~ di & ~ ei & ~ ii) ;

assign	or131  = (gi & hi & ji) | (fi & hi & ji) | (ior134);
assign	or132  = (fi & gi & ji)	| (~ fi & ~ gi & ~ hi)	| (~ fi & ~ gi & hi & ji);
assign	or133  = (~ fi & ~ hi & ~ ji)	| (ior134)	| (~ gi & ~ hi & ~ ji) ;
assign	or134  = (~ gi & ~ hi & ~ ji)	| (fi & hi & ji)	| (ior134) ;
	
assign	xf = or131	| or132 ;
assign	xg = or132  | or133 ;
assign	xh = or132	| or134 ;
	
always @ (posedge clk or negedge rst)
		begin
				if (!rst)
						begin
								fo<=1'b0;
								go<=1'b0;
								ho<=1'b0;
						end
				else
						begin
								fo<=xf ^ fi;
								go<=xg ^ gi;
								ho<=xh ^ hi;	
						end
		end		

assign  out = {ho,go,fo,eo,do,co,bo,ao}; 

endmodule
